(*DONT_TOUCH = "TRUE"*)
module ad_top(
	input					sys_clk		,
	input					rst_n		,
	
	input	[15:0]			Din	,
	input					busy		,
	input					Fdata		,

	output					Cs			,
	output					Rd			,
	output					cvtA		,
	output					cvtB		,
	output					phy_rst		,
	output					clk_50m		,
	output		[15:0]		ch1
);

wire 			Fpga_Rst;
wire 				en			;

wire	[15:0]	ch2		;
wire	[15:0]	ch3		;
wire	[15:0]	ch4		;
wire	[15:0]	ch5		;
wire	[15:0]	ch6		;
wire	[15:0]	ch7		;
wire	[15:0]	ch8		;


PLL u_pll(
	// Clock out ports
	.clk_out1(clk_50m),     // output clk_out1
	// Status and control signals
	.locked(locked),       // output locked
	// Clock in ports
	.clk_in1(sys_clk)      // input clk_in1
);

generate_en en_inst
(
	.clk		(clk_50m),
	.rst_n	(rst_n),
	.en_o		(en)
);

AD7606_ctrl 
AD_inst
(
	//system signals
	.clk		(clk_50m),
	.rst_n	(rst_n)	,
	//time control
	.en		(en)		,
	//contrl start
	.start	(1'b1)	,
	//phy interface and signals
	.busy		(busy)	,
	.fdata	(Fdata)	,
	.cvtData	(Din),
//	.ch_A_B_n(1'b1)	,
	
	.cs		(Cs)		,
	.rd		(Rd)		,
	.cvtA		(cvtA)	,
	.cvtB		(cvtB)	,
	// output	reg					refSlt	,
	.phy_rst	(phy_rst),
	
	.ch1		(ch1)	,
	.ch2		(ch2)	,
	.ch3		(ch3)	,
	.ch4		(ch4)	,
	.ch5		(ch5)	,
	.ch6		(ch6)	,
	.ch7		(ch7)	,
	.ch8		(ch8)	,
	.update	()	,
	.phy_busy()	
);

endmodule